Ambipolar Gate Bias in VOFETs

Why is it important to use ambipolar gate bias in VOFET?

… you can improve the VOFET on-off ratio …

The gate modulation (created by the capacitive cell) in a VOFET occurs through the pores in the permeable intermediate electrode (IE). So, the total current density in the “diode cell” (see figure) can be generated by  the current from the intermediate electrode region without pores more the current  from the region through the pores of the intermediate electrode. How?

VOFET with nanowires as permeable intermediate electrode

Depending on the semiconductor type and energy barrier formed from the VOFET structure, you can applied a unipolar or ambipolar source-drain (Vds) voltage. That is a well know feature widely discussed in the literature, because of this it will not be discussed here again. So, the main point of view here is, how is it possible to improve the on-off ratio in VOFETs using a ambipolar gate biasing?

When no gate voltage is applied (Vg= 0V) -> Actually, the VOFET architecture works as a simple diode cell. There is a current density flowing from (or to) the nanowires intermediate electrode to (or from) the top electrode. Frequently, this gate voltage value is set as a off-state of VOFET. But,  in many situation the off-current can be decreased when a backward gate voltage is applied. Thereafter the on-“off” ratio will be increased. How?

I) To form the VOFET “on-state” – a direct gate voltage is applied -> this gate voltage polarization will induce charge carriers in the IE/semiconductor interface in such a way that will increase the current density. This means that for n-type channel the gate voltage must induce negative charge carriers in the pores region and for p-type channel the gate voltage must induce positive charge carriers in the pores region. The output current is a sum from the current obtained when Vg=0V (simple diode cell) more the current density created in the IE pores/channel interface. (IE=intermediate electrode);

II) To form  the VOFET “off-state” – a backward gate voltage is applied -> The gate voltage induced charge carriers in the IE/semiconductor will “close” the pores current density. The total current density will be decreased. In many situation this current density is lower than the “simple diode current density (Vg=0V)” because the “inverse” charge carriers induced in the channel change/increase the energy barrier in the pores region and edges pores!

You can find a description about this phenomena in this literature…

https://doi.org/10.1007/s00339-018-1982-x

Figure from reference “Vertical organic field effect transistor: on–off state definition related to ambipolar gate biasing”. Keli Seidel et al. (2018). https://doi.org/10.1007/s00339-018-1982-x

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